jlink接口图

时间：2021-10-04 14:58:22

关键字： jlink 接口

[导读]JLink、JTAG接口详细图解

1脚：通常连接到目标板的vdd，用来检测目标系统是否供电;检测原理上图中有简单的说明。

2脚：原版的JLink这个引脚没有使用，不提供Vsupply输出，而很多改造版的JLink通过跳线选择从该引脚输出3.3V的电压给外边，我的就是这样的。

可以到网上找JLink的原理图看看。

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0517b/Cjaeccji.html

JTAG interface signals

The following table describes the signals on the JTAG interfaces:

Table 1. JTAG signals

SignalI/ODescription

DBGACK-This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system. It is recommended that this signal is pulled LOW on the target.

DBGRQ-This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. The RVI software maintains this signal as LOW.

When applicable,RVI uses the scan chain 2 of the processor to put the processor in debug state. It is recommended that this signal is pulled LOW on the target.

GND-Ground.

nSRSTInput/outputActive Low output from RVI to the target system reset, with a 4.7kΩ pull-up resistor for de-asserted state. This is also an input to RVI so that a reset initiated on the target can be reported to the debugger.

This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

nTRSTOutputActive Low output from RVI to the Reset signal on the target JTAG port, driven to the VTref voltage for de-asserted state. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

RTCKInputReturn Test Clock signal from the target JTAG port to RVI. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. RVI provides Adaptive Clock Timing, that waits for TCK changes to be echoed correctly before making more changes. Targets that do not have to process TCK can ground this pin.

RTCK is not supported in Serial Wire Debug (SWD) mode.

TCKOutputTest Clock signal from RVI to the target JTAG port. It is recommended that this pin is pulled LOW on the target.

TDIOutputTest Data In signal from RVI to the target JTAG port. It is recommended that this pin is pulled HIGH on the target.

TDOInputTest Data Out from the target JTAG port to RVI. It is recommended that this pin is pulled HIGH on the target.

TMSOutputTest Mode signal from RVI to the target JTAG port. This pin must be pulled HIGH on the target so that the effect of any spurious TCKs when there is no connection is benign.

VsupplyInputThis pin is not connected in the RVI unit. It is reserved for compatibility with other equipment to be used as a power feed from the target system.

VTrefInputThis is the target reference voltage. It indicates that the target has power, and It must be at least 0.628V. VTref is normally fed from Vdd on the target hardware and might have a series resistor (though this is not recommended). There is a 10kΩ pull-down resistor on VTref in RVI.

ARM系统的JTAG接口的设计不当往往使硬件系统无法调试，所以在设计ARM系统前要先熟悉ARM系统的JTAG接口的定义和常见问题。

1.ARM系统的JTAG接口是如何定义的? 每个PIN又是如何连接的?

下图是JTAG接口的信号排列示意：

接口是一个20脚的IDC插座。下表给出了具体的信号说明：

表 1 JTAG引脚说明

序号信号名方向说明

1VrefInput接口电平参考电压，通常可直接接电源

2VsupplyInput电源

3nTRSTOutput(可选项) JTAG复位。在目标端应加适当的上拉电阻以防止误触发。

4GND--接地

5TDIOutputTest Data In from Dragon-ICE to target.

6GND--接地